F. Poh KS, Tan Hien Boon, Krishnamoorthi Sivalingam, Lim Beng Kuan
Leadframe CSP package had been well known to be a superior choice for high-speed application where high thermal performance is desired. With the advancement in technology trend, there is more increasing demand for higher thermal performance in miniature package to dissipate heat and improve the device performances. This paper describes the cost-effective development and material characterisation of high power quad flat no lead (HQFN) package that had successfully been qualified in United Test and Assembly Center (UTAC) at JEDEC level 2A with full environmental testing. The assembly processes are leveraged from the standard QFN assembly with only the inclusion of silicon lid attached over the integrated chip, hence, creating an addition heat dissipation path to the top surface. The package thermal performance is dependent on the surface area of the exposed lid, which is governed by the die size or bond pad layout. Package larger than HQFN 7×7 size can achieve higher thermal performance than the exposed top paddle's smart metal chip scale package (SMCSP). Existing leadframe can be used for this HQFN package and its outline conformed to the JEDEC registered outline MO221 for QFN packages.